ATMEGA324A-MCHR【PDF 45/160 页】IC MCU AVR 32K 20MHZ 44QFN

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Sheet目录3761

41页 42页 43页 44页 [45页]46页 47页 48页 49页

139

8272E–AVR–04/2013

ATmega164A/PA/324A/PA/644A/PA/1284/P

temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit

registers. See “Accessing 16-bit Registers” on page 113.

16.12.11 ICR3H and ICR3L – Input Capture Register 3

The Input Capture is updated with the counter (TCNT3) value each time an event occurs on the

ICPn pin (or optionally on the Analog Comparator output for Timer/Counter3). The Input Capture

can be used for defining the counter TOP value.

The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read

simultaneously when the CPU accesses these registers, the access is performed using an 8-bit

temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit

registers. See “Accessing 16-bit Registers” on page 113.

16.12.12 TIMSK1 – Timer/Counter1 Interrupt Mask Register

Bit 7:6 – Reserved

These bits are unused and will always read as zero.

Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt

Vector (see “Interrupts” on page 61) is executed when the ICF1 Flag, located in TIFR1, is set.

Bit 4:3 – Reserved

These bits are unused and will always read as zero.

Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding

Interrupt Vector (see “Interrupts” on page 61) is executed when the OCF1B Flag, located in

TIFR1, is set.

Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding

Interrupt Vector (see “Interrupts” on page 61) is executed when the OCF1A Flag, located in

TIFR1, is set.

Bit

76543210

(0x97)

ICR3[15:8]

ICR3H

(0x96)

ICR3[7:0]

ICR3L

Read/Write

R/W

Initial Value

00000000

Bit

(0x6F)

–

–ICIE1

–

OCIE1B

OCIE1A

TOIE1

TIMSK1

Read/Write

R/W

Initial Value

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